Consumer electronics of today, such as personal video players and digital cameras, utilize more memory than the mainframe computers of the nineteen seventies and eighties. Non-volatile memory devices generally include arrays of memory cells that retain information without electrical power being supplied to the memory device. The memory cells maintain information in an “off” or an “on” state, also referred to as “0” and “1”. Each memory cell can be “written” (programmed) with information, “read”, and “erased”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
The use of portable computer and electronic devices has greatly increased demand for non-volatile memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity non-volatile memory devices (e.g., flash memory, smart media, compact flash, and the like).
Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, the scaling of conventional MOSFET based memory devices is approaching fundamental physical limits. Therefore, there is a need to overcome the physical limits of conventional memory devices.
One approach to increasing memory device density is the use of a metal-insulator-metal (MIM) memory cell. A MIM cell may include a first electrode, an active resistive layer on the first electrode, and a second electrode on the active layer. Initially, assuming that the memory cell is un-programmed, in order to program the memory cell, ground is applied to the first electrode, while a positive voltage is applied to the second electrode, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory cell from a higher to a lower electrical potential in the direction from the second electrode to the first electrode. Upon removal of such potential the memory cell remains in a conductive or low-resistance state having an on-state resistance.
In the read step of the memory cell in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory cell from a higher to a lower electrical potential in the direction from the second electrode to the first electrode. This electrical potential is less than the electrical potential Vpg applied across the memory cell for programming (see above). In this situation, the memory cell will readily conduct current, which indicates that the memory cell is in its programmed state.
In order to erase the memory cell, a positive voltage is applied to the first electrode, while the second electrode is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory cell from a higher to a lower electrical potential in the direction from the first electrode to the second electrode.
In the read step of the memory cell in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory cell from a higher to a lower electrical potential in the direction from the second electrode to the first electrode as described above. With the active layer in a high-resistance or substantially non-conductive state, the memory cell will not conduct significant current, which indicates that the memory cell is in its erased state.
Typically, programming of a memory cell is achieved by applying a fixed number of pulses at constant voltage across the memory cell. Erasing the memory cell may be problematic because of physical differences between memory cells in a memory device array. The electrical potential required to achieve programming can vary between memory cells causing individual memory cells in the memory device array to be programmed to different levels. Applying a constant programming electrical potential, to a memory cell which is substantially greater than that required for programming, can result in over-programming making it extremely difficult to erase. Therefore, what is needed is an approach wherein, while proper programming of the memory cell is achieved erasure of the memory can be reliably performed in a rapid fashion.
Alternative erase mechanisms in MIM cells include the application of heat or light of an appropriate frequency in order to release trapped charges that change the insulating properties of the resistive layer. Relatively uniform intensity and wide distribution of light is believed to be easier to provide than heat in a silicon die or packaging system structure. Therefore, light based (optical) erase offers an easier to implement ability to erase large areas of a MIM memory array simultaneously. Optical erase may also offer the ability to erase over-programmed cells. Optical erase can be used in addition to or in replacement of the above described electrical erase mechanism.
Furthermore, the memory cell as thus far shown and described is capable of adopting two states, i.e., a first, conductive state, or “on” state, and a second, substantially non-conductive, or “off” state. Each memory cell thus can include information as to the state of a single bit, i.e., either 0 or 1. However, it would be highly desirable to be able to provide a memory cell which is capable of adopting any of a plurality of states, so that, for example, in the case where four different states of the memory cell can be adopted, two bits of information can be provided as chosen (for example first state equals 00, second state equals 01, third state equals 10, fourth state equals 11). This multi-level (ML) memory technology can significantly improve memory density and reduce the cost per bit.
MIM cells can significantly increase the density of a memory device as compared to conventional MOSFET based memory devices. An optical erase memory structure may provide parallel erase of many single or multi-bit MIM cells in order to provide rapid and reliable erase of high density MIM devices.
In view of the increasing demand for large amounts of memory in personal electronic devices, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance to meet competitive pressures in the non-volatile memory market, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.